In general, the addressable memory space of a memory system can be defined by the number of available address bits and/or the number of available chip select signals.
The addressable memory space in a memory system can be generally characterized as a two dimensional memory space with two orthogonal dimensions wherein the first dimension is defined by a first set of one or more address bits, and the second dimension is defined by one or more chip select signals. For example, FIG. 1 schematically illustrates a memory system 100 having a conventional two-dimensional memory space architecture with a first set of 14 address bits and four chip select signals. The memory system 100 of FIG. 1 shows a configuration of a nibble or four-bit slice of memory space comprising four DRAM devices 102 (e.g., x4 DRAM devices). Each DRAM device receives a chip select signal and four chip select signals can uniquely access one of the four DRAM devices 102 with the common address and command signals.
Increasing the number of address bits generally expands the memory space of the first dimension of the address space, and increasing the number of chip select signals generally expands the memory space of the second dimension of the address space. For example, if a system memory controller supports a fixed number of chip select signals but can optionally support one or more additional address bits, the memory space for this example system memory controller can support higher density memory devices (e.g., dynamic random access memory devices or DRAM devices) because the additional address bits allow for accessing higher density memory devices. However, such an example system memory controller generally can not access more memory devices due to the fixed number of chip select signals because each memory device generally has a corresponding chip select signal.